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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC * The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4094B MSI 8-stage shift-and-store bus register Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 8-stage shift-and-store bus register DESCRIPTION The HEF4094B is an 8-stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel buffered 3-state outputs O0 to O7. The parallel outputs may be connected directly to common bus lines. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (EO) signal is HIGH. HEF4094B MSI Two serial outputs (Os and O's) are available for cascading a number of HEF4094B devices. Data is available at Os on positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at O's on the next negative-going clock edge and provides cascading HEF4094B devices when the clock rise time is slow. Fig.2 Pinning diagram. HEF4094BP(N): 16-lead DIL; plastic (SOT38-1) HEF4094BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4094BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING D CP Fig.1 Functional diagram. STR data input clock input strobe input EO Os, O's O0 to O7 output enable input serial outputs parallel outputs FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... January 1995 3 Fig.3 Logic diagram. Product specification Fig.4 One D-latch. Philips Semiconductors 8-stage shift-and-store bus register HEF4094B MSI Philips Semiconductors Product specification 8-stage shift-and-store bus register FUNCTION TABLE INPUTS CP EO L L H H H H Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. 5. = positive-going transition = negative-going transition STR X X L H H H D X X X L H H PARALLEL OUTPUTS O0 Z Z nc L H nc On Z Z nc On-1 On-1 nc SERIAL OUTPUTS Os O'6 nc O'6 O'6 O'6 nc O's nc O7 nc nc nc O7 HEF4094B MSI 6. Z = high impedance off state 7. nc = no change 8. O'6 = the information in the seventh shift register stage At the positive clock edge the information in the 7th register stage is transferred to the 8th register stage and the Os output. AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; input transition times 20 ns VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (W) 2100 fi + (foCL) x VDD2 9700 fi + (foCL) x 26 000 fi + (foCL) x VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 4 Philips Semiconductors Product specification 8-stage shift-and-store bus register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP Os HIGH to LOW 5 10 15 5 LOW to HIGH CP O's HIGH to LOW 10 15 5 10 15 5 LOW to HIGH CP On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH STR On HIGH to LOW 10 15 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 135 65 50 105 50 40 105 50 40 105 50 40 165 75 55 150 70 55 110 50 35 100 45 35 60 30 20 60 30 20 270 130 100 210 100 80 210 100 80 210 100 80 330 150 110 300 140 110 220 100 70 200 90 70 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX. HEF4094B MSI TYPICAL EXTRAPOLATION FORMULA 108 ns + (0,55 ns/pF) CL 54 ns + (0,23 ns/pF) CL 42 ns + (0,16 ns/pF) CL 78 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 78 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 78 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL 138 ns + (0,55 ns/pF) CL 64 ns + (0,23 ns/pF) CL 47 ns + (0,16 ns/pF) CL 123 ns + (0,55 ns/pF) CL 59 ns + (0,23 ns/pF) CL 47 ns + (0,16 ns/pF) CL 83 ns + (0,55 ns/pF) CL 39 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL January 1995 5 Philips Semiconductors Product specification 8-stage shift-and-store bus register AC CHARACTERISTICS VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns VDD V 3-state propagation delays Output enable times EO On HIGH LOW Output disable times EO On HIGH LOW Minimum clock pulse width LOW Minimum strobe pulse width HIGH Set-up times D CP Hold times D CP Maximum clock pulse frequency 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax thold tsu tWSTRH tWCPL 60 30 24 40 30 24 60 20 15 5 20 20 5 11 14 tPLZ tPHZ tPZL tPZH 40 25 20 40 25 20 75 40 30 80 40 30 30 15 12 20 15 12 30 10 5 -15 5 5 10 22 28 80 50 40 80 50 40 150 80 60 160 80 60 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz SYMBOL MIN. TYP. MAX. HEF4094B MSI January 1995 6 Philips Semiconductors Product specification 8-stage shift-and-store bus register HEF4094B MSI Fig.5 Timing diagram. APPLICATION INFORMATION Some examples of applications for the HEF4094B are: * Serial-to-parallel data conversion * Remote control holding register Fig.6 Remote control holding register. January 1995 7 |
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